To sample broadband signals of e.g. satellite receivers, track and hold (T/H) circuits are needed with a bandwidth of about 1 GHz and linearity above 50 dB or the like. For software defined radios an even larger bandwidth is desired. To be able to embed the T/H circuit together with an analogue digital converter (ADC) in a digital integrated circuit (IC), the power consumption of the T/H circuit and the ADC should be limited to a few hundred milliwatts. Time-interleaving is a good way of combining power efficiency with high speed. However, a time-interleaved T/H circuit needs a signal bandwidth per channel far beyond the sample-rate of an individual channel. Moreover, it requires matching between its channels. The T/H circuit may be a successor as described in document “A 1.6 GS/s,16 times interleaved track & hold with 7.6 ENOB in 0.12 μm CMOS,” S. M. Louwsma, E. J. M. van Tuijl, M. Vertregt, P. C. S. Scholtens and B. Nauta, Proc. ESSCIRC, pp 343-346, September 2004, comprising improved bandwidth, linearity and channel matching.
In document “A 1 GS/s 11b Time-Interleaved ADC in 0.13 μm CMOS,” S. Gupta, M. Choi, M. Inerfield, J. Wang, ISSCC Dig. Tech. Papers, pp 264-265, February 2006, a technique to prevent timing errors in a time-interleaved T/H circuit is presented. It uses a front-end sampling switch which is closed only half a period of the master clock. A disadvantage of this method is the decrease in bandwidth. To increase the bandwidth, the switch can be made very large, but then charge injection errors become a problem.
Another technique is the use of the master clock to synchronize the different sampling instants as in document “A Dual-Mode 700-Msample/s 6-bit 200-Msamples/s 7-bit A/D Converter in a 0.25 μm Digital CMOS Process,” K. Nagaraj et al., IEEE JSSC, vol. 35, pp 1760-1768, December 2000, which achieves good timing alignment, and does not have the disadvantages of a front-end sample switch.
In applications wherein supply-noise degrades performance, current mode logic (CML) is commonly used due to the fact that the generated supply noise is low. CML uses differential signalling, with signals swings about half the supply voltage. For applications wherein a full swing signal is required, i.e. a sample switch in a T/H circuit, the CML signals have to be converted to full-swing signals. This can be done by an embodiment according to prior art shown in FIG. 13. As can be seen from FIG. 13, eight transistor elements are required within the shown embodiment.
Depending on actual transistor mismatch, the circuit shown in FIG. 13 generates skew, which is different for every instance of the circuit. In the embodiment of the circuit shown in FIG. 13, a lot of transistors contribute to the skew variation. Although scaling of these transistors reduces this variation, the power consumption is increased and the sizes may even become unpractical for high performance applications. The power consumption may become too large or the supply-noise generated by the circuit may become too large.
It is one object of the present application to provide an apparatus, wherein the influence of the skew is significantly reduced. A further object is to avoid an influence of the local supply voltage in the moment of transition. A further object is to reduce power consumption. Another object is to reduce generated supply-noise. Another object is to reduce a delay. A further object is to reduce the jitter added to the present apparatus.